The present invention relates generally to direct digital synthesizers, and more particularly to direct digital synthesizers employing noise shaping to reduce phase truncation noise.
Frequency synthesizers are known in the art. These devices typically generate waveforms (such as a sine wave, square wave, triangle, and the like) that are selectable over a wide frequency range and yet maintain high accuracy and frequency stability. Indirect synthesis methods typically employ a voltage-controlled oscillator (VCO) that is part of a phase-locked loop (PLL). A selectable frequency divider is set to provide the desired ratio between the output frequency and the crystal reference frequency. The output of the frequency divider is fed to one input of a phase detector, while the other input receives the output from the crystal reference frequency. The output of the phase detector is used to control the VCO. Fractional frequency division can be obtained by dynamically selecting the division ratio to alternate between values N and N+1 for suitable time intervals so that the average ratio is the desired fraction.
Direct digital synthesis of waveforms utilizes a different technique for generating a desired output. As illustrated in FIG. 1(a), a conventional direct digital synthesizer (DDS) 100 employs a phase accumulator 101 and a look-up table (LUT) 103. The accumulator 101 has an n-bit output which is incremented by a phase increment 105 with each assertion of the clock input 107. The LUT 103 may be, for example, a read only memory (ROM) having
2.sup.m k-bit wide storage locations into which have been stored corresponding sample values of the waveform to be generated. It is assumed, throughout this entire specification, that the number of stored samples is greater than the minimum number that would be necessary to generate the desired frequency, so that all of the devices described herein operate in an oversampled environment. The addresses for the LUT 103 are supplied by the m most significant bits of the n-bit output of the accumulator 101. The output of the LUT 103 is supplied to a digital to analog converter (DAC) 109, whose output is the desired analog waveform having a frequency that is a function of the clock frequency (f.sub.clk) as well as the phase increment 105.
The conventional DDS 100 suffers from the introduction of noise at two places. First, because the output of the LUT 103 is a finite width, a quantization error, e.sub.k, is introduced. A second error, e.sub.p, is introduced as a result of the truncation of the n-bit phase word to only m-bits for use in addressing the LUT 103. As described, for example, in P. O'Leary and F Maloberti, "A Direct-Digital Synthesizer with Improved Spectral Performance", IEEE Transactions On Communications Vol. 39, No. 7, pp. 1046-48 (July 1991), the entire text of which is incorporated herein by reference, the output of the DDS 100 is given by the following equation: ##EQU1## where: f.sub.gen is the generated frequency;
e.sub.p (i) is the error associated with the phase truncation from n bits at the accumulator 101 and m address bits at the LUT 103; and PA1 e.sub.k (i) is the quantization error due to the finite LUT data word (k bits).
As further described in P. O'Leary et al. "Oversampling Data Conversion Applied to Data Modulation", International Conference on Analogue to Digital and Digital to Analog Conversion pp. 124-129, 17-19 September 1991 (Swansea UK, IEE London, UK 1991), the text of which is incorporated herein by reference, it has been necessary to dimension the LUT 103 with an address bus one bit wider than the data bus, to ensure that the output error is dominated by the LUT data width and not by the address truncation. For high precision sine waves, this requires a very large LUT 103, because the LUT size increases exponentially in powers of 2 with the address width but only linearly in the number of data bits.
To overcome this disadvantage, O'Leary and Maloberti observe that the truncation of the n phase bits to m bits for use as a LUT address corresponds to quantization, and that if the frequency being generated is low with respect to the used clock frequency, then there is an intrinsic oversampling. Thus, they disclose the use of a noise shaping technique, shown in FIG. 1(b), to reduce the effects of the phase truncation. The noise shaper 115 comprises an m-bit wide adder 111 and a clocked register 113 coupled together to form a second accumulator. The m-bit output of the phase accumulator 101 is supplied as one input to the adder 111. The most significant p bits of the adder 111 are supplied as an address to the LUT 103. The remaining m-p bits from the output of the adder 111 are clocked into the register 113, the output of which is fed back to the second input of the adder 111. As a result of this arrangement, the phase error resulting from phase truncation is accumulated, and used to correct the LUT address, in what amounts to linear (first-order) noise shaping. O'Leary and Maloberti state that a quadratic interpolation between two consecutive LUT addresses could alternatively be used. In either case, however, the O'Leary technique operates to increase noise suppression around the carrier frequency without significantly increasing the bandwidth of noise suppression. It would be desirable to increase the noise suppression bandwidth in order to allow more information to be conveyed for a given signal-to-noise ratio (S/N), and also to facilitate anti-alias filtering.
It is a further goal, in DDS design, to reduce the size of the DAC 109 so that it will operate at higher speeds without sacrificing output accuracy. However, in conventional practice there is a tradeoff between quantization accuracy and speed of operation. Thus, operation at higher speeds has required a smaller quantization. The O'Leary technique fails to address this problem as well.
DDS's are frequently used in the field of communications. One such use is in the area of modulation. It is well known that different "channels" of information can be carried simultaneously in the radio frequency spectrum through the use of Frequency Division Multiple Access (FDMA), whereby each baseband signal (representing the desired information to be communicated) is superimposed onto (i.e., modulates) a particular one of a number of higher frequency carrier signals. The modulated carrier signal can then be transmitted over a medium (e.g., coaxial cable, wires, space) that is simultaneously conveying other modulated signals having different carrier frequencies. Any number of different modulation techniques can be used, all of which can be generally described by means of a complex baseband signal.
To perform the modulation, two different approaches can be taken. The traditional approach is to utilize analog circuitry that causes the baseband signal to modulate the carrier frequency in accordance with the selected modulation technique. An alternative approach is to convert (or otherwise construct) the baseband signal into a digitized stream of complex baseband data, multiply by complex carrier signal data, and then convert the in-phase (or antiphase) sum of the products into an analog signal.
Either of the above two methods allows the construction of complex spectral outputs, but the digital (i.e., second) approach allows software control of the modulation. Software is advantageous because it can be modified at low relative cost. Both approaches, however, produce outputs containing the product of noise powers present in both the carrier and data inputs. Thus, where the digital method of modulation has been used, it has been necessary to use larger DACs than would otherwise be desirable, in order to reduce the amount of noise that shows up in the modulated signal.